1. Field of the Invention
This invention relates to packet transmission between packet switching systems and more particularly to a cell synchronizing apparatus and method for synchronizing packet switching systems using a synchronization cell.
2. Description of the Related Art
FIG. 4 shows one example of the structure of a packet switching system. In FIG. 4, a packet switching system 100 includes terminal interfaces 11, 12 and 13; a line interface 14; a controller 15; a control bus 16; and a data bus 17. Similarly, a packet switching system 200 includes terminal interfaces 21, 22 and 23; a line interface 24; a controller 25; a control bus 26; and a data bus 27. The packet switching systems 100 and 200 are connected by lines 18a and 18b. The packet switching system 100 has terminals 31, 32 and 33 connected therewith while the packet switching system 200 has terminals 41, 42 and 43 connected therewith.
In such arrangement, assume that, for example, telephone communication is made between the terminals 31 and 41 using the switching systems 100 and 200. Data transmitted by the terminal 31 is assembled as a data packet having a fixed length, namely, a data cell as shown in FIG. 5(a), at the terminal interface 11 of the switching system 100. The data cell 50 includes a destination address 51 and data 52. The address is added at the terminal interface 11. The data cell 50 is delivered to the line interface 14 via the data bus 17 of the switching system 100 and then to the line interface 24 of the called switching system 200 through the line 18a. The line interface 24 is synchronized with the line interface 14 such that a data cell can be extracted from an incoming train of data. In accordance with the destination address 51, the data cell extracted at the line interface 24 is sent via the data bus 27 to the terminal interface 21 where the data cell is transformed into a train of data, which is sent to the terminal 41.
A synchronization cell is sent from the line interface 14 to the line interface 24 via the line 18a for cell synchronization between the line interfaces 14 and 24. The synchronization cell 60 includes a predetermined synchronization pattern 61 as shown in FIG. 5(b). As seen in FIG. 5(b), synchronization cell 60 contains a single synchronization pattern 61 in a header portion of the synchyronization cell.
The synchronization cell(s) 60 is sent in such situations in which there is a time period during which no data cell 50 is sent as shown in FIG. 6(b) or after data cells are sent successively for a predetermined interval after the synchronization cell 60 is sent as shown in FIG. 6(a).
The line interface 24 detects the synchronization pattern of the synchronization cell to establish the cell synchronization. A conventional cell synchronization circuit has a structure as shown in FIG. 7. In FIG. 7, a synchronization pattern detector 71 detects the synchronization pattern 61 contained in the synchronization cell 60 from the received data D1 and outputs a synchronization pattern detection signal S1 upon detection of the synchronization pattern 61, is then applied through AND gates 72; 73 to a reset terminal R of a cell length counter 74 and has the effect of resetting counter 74. After being reset, the counter 74 is counted up by a clock CK and outputs a cell length count signal S2 each time it counts clocks corresponding to the length of the synchronization cell.
If the counter 74 is reset at the position of a correct synchronization pattern 61, the synchronization pattern detection signal S1 and the cell length count signal S2 appear at the same timing, so that the signal S2 closes AND gate 73 and no reset signal enters the counter 74. When the synchronization pattern detector 71 detects a predetermined number of successive synchronization patterns 61 at their correct positions, a synchronization protection unit 75 determines that synchronization is correctly established at that position. At such time, unit 75 outputs gate signal S3 which is effective to close the AND gate 72. That is, signal S3 has a logic value effective to prevent propagation of signal S1 through AND gate 72. As a result, no synchronization pattern detection signal S1 is applied through the AND gate 73 to the reset terminal R of the counter 74 and hence the counter 74 is not reset. The output of the synchronization protection unit 75 opens, i.e., renders conductive a NOR gate 76 and the cell length count signal S2 from the counter 74 is output as a synchronization signal S0.
If the counter reset does not occur at the position of the correct synchronization pattern , the timing at which the cell length count signal S2 closes, i.e., renders nonconductive, the AND gate 73 differs from the timing at which the reset signal appears and thus the counter 74 is again reset. That is, as seen in FIG. 7, signal S2 is inverted to prevent propagation of signal S1 through AND gate 73. These operations are repeated until the counter 74 is reset at the position of the correct synchronization pattern to thereby achieve the cell synchronization.
In this arrangement, even if the counter 74 is reset at the position of the correct synchronization pattern, a situation may occur in which the synchronization pattern detector 71 detects a synchronization pattern at a position other than the position of the correct synchronization pattern before the synchronization protection unit 75 determines that synchronization is maintained correctly at the position of the correct synchronization pattern. In that situation, the synchronization pattern detector 71 outputs the synchronization pattern detection signal S1 which will reset the counter 74 and the synchronization protection unit 75 without being blocked at the AND gate 73 by the cell length count signal S2. Thus, the processes of the establishment of synchronization is required from the beginning. This would undesirable increase at the time required for established of synchronization.
An attempt could be made which increases the length of bits used in the synchronization pattern to prevent the detection of a synchronization pattern at a position other than the position of the correct synchronization pattern. However, this process only reduces the possibility of detection of the synchronization pattern at a position other than the position of the correct synchronization pattern, but does not eliminate the possibility completely.
As mentioned above, if the conventional cell synchronization system detects a synchronization pattern at a position other than the position of the correct synchronization pattern during the transient interval from an asynchronous state to the establishment of synchronization, it resets the synchronization protection unit, so that the establishment of synchronization is required from the beginning to thereby increase the time required for establishment of synchronization undesirably.